tc74vhct9273p/ft/fk 2009-07-01 1 toshiba cmos digital integrat ed ci rcuit silicon monolithic tc74vhct9273p,tc74vhc t9273ft,TC74VHCT9273FK octal d-type flip flop with clear the tc74vhct9273 is an advanced high speed cmos octal d-type flip flop fabricated with silicon gate c2mos technology. it achieves the high speed operation similar to equivalent bipolar schottky ttl while maintaining the cmos low power dissipation. the input voltage are compatible with ttl output voltage. this device may be used as a level converter for interfacing 3.3 v to 5 v system. information signals applied to d inputs are transferred to the q outputs on the positive going edge of the clock pulse. when the clr input is held ?l?, the q outputs are at a low logic level independent of the other inputs. the clr input and ck input have hysteresis between the positive-going and negative-going thresholds. thus the tc74vhct9273 is capable of squari ng up transitions of slowly changing input signals and pr ovides an improved noise immunity. it is easy to wire on the board because input terminals are at the opposite side of output terminals. an input protection circuit en sures that 0 to 5.5 v can be applied to the input pins withou t regard to the supply voltage. features ? high speed: f max = 185 mhz (typ.) at v cc = 5 v ? low power dissipation: i cc = 4 a (max) at ta = 25c ? compatible with ttl inputs : v il = 0.5 v (max) v ih = 2.1 v (min) ? power down protection is provided on all inputs. ? balanced propagation delays: t plh ? t phl ? function compatible with 74vhc273 ? input terminals are at the opposi te side of output terminals tc74vhct9273p tc74vhct9273ft TC74VHCT9273FK weight dip20-p-300-2.54a : 1.30 g ( typ.) tssop20-p-0044-0.65a : 0.08 g ( typ.) vssop20-p-0030-0.50 : 0.03 g ( typ.)
tc74vhct9273p/ft/fk 2009-07-01 2 pin assignment iec logic symbol truth table inputs output clr d ck q function l x x l clear h l l D h h h D h x q n no change x: don?t care system diagram v cc 16 q1 q2 q3 15 14 clr 1 2 3 4 5 6 7 d3 d4 d5 d6 d7 q4 8 q7 13 q5 q6 (top view) d1 d2 12 9 d8 gnd 10 ck 11 q8 19 18 17 20 (11) (1) (2) (4) (3) d1 1d d3 d2 (6) (5) (7) d5 d4 (19) (17) (15) q1 q3 q5 (18) (16) (14) q2 q4 q6 r c 1 ck clr d6 (8) (9) d7 (13) q7 (12) q8 d8 ck clr q1 1 11 q2 2 19 q3 3 18 q4 4 17 q7 5 16 q8 8 13 9 12 ck q d ck q d ck q d ck q d ck q d ck q d d1 d2 d3 d4 d7 d8 r r r r r r q5 6 15 ck q d d5 r q6 7 14 ck q d d6 r
tc74vhct9273p/ft/fk 2009-07-01 3 absolute maximum ratings (note1) characteristics symbol rating unit supply voltage range v cc ?0.5 to 7.0 v dc input voltage v in ?0.5 to 7.0 v dc output voltage v out ?0.5 to v cc + 0.5 v input diode current i ik ?20 ma output diode current i ok 20 ma dc output current i out 25 ma dc v cc /ground current i cc 75 ma power dissipation p d 500 (dip) (note 2)/180(tssop/vssop) mw storage temperature t stg ?65 to 150 c note 1: exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in ic performance or even destruction. using continuously under heavy loads (e.g. the app lication of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temper ature/current/voltage, etc. ) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (?handling precautions?/?derating concept and methods?) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). note 2: 500 mw in the range of ta 40 to 65c. from ta 65 to 85c a derating factor of 10 mw/c shall be applied until 300 mw. operating ranges (note) characteristics symbol rating unit supply voltage v cc 4.5 to 5.5 v input voltage v in 0 to 5.5 v output voltage v out 0 to v cc v operating temperature t opr ?40 to 85 c note: the operating ranges must be maintained to ensure the normal oper ation of the device. unused inputs must be tied to either v cc or gnd.
tc74vhct9273p/ft/fk 2009-07-01 4 electrical characteristics dc characteristics test condition ta = 25c ta = 40 to 85c characteristics symbol v cc (v) min typ. max min max unit high-level input voltage v ih ? 4.5 5.5 ? ? ? ? 1.90 2.10 ? ? 1.90 2.10 low-level input voltage v il ? 4.5 5.5 0.50 0.60 ? ? ? ? 0.50 0.60 ? ? v hysteresis voltage (ck clr ) v h ? 4.5 5.5 0.40 0.40 ? ? 1.40 1.50 0.40 0.40 1.40 1.50 v i oh = 50 p a 4.5 4.4 4.5 ? 4.4 ? high-level output voltage v oh v in = v il i oh = 8 ma 4.5 3.94 ? ? 3.80 ? i ol = 50 p a 4.5 ? 0.0 0.1 ? 0.1 low-level output voltage v ol v in = v ih i ol = 8 ma 4.5 ? ? 0.36 ? 0.44 v input leakage current i in v in = 5.5 v or gnd 0~ 5.5 ? ? 0.1 ? 1.0 p a i cc v in = v cc or gnd 5.5 ? ? 2.0 ? 20.0 p a quiescent supply current i cct per input: v in = 3.4 v other input: v cc or gnd 5.5 ? ? 1.35 ? 1.50 ma timing requirements (input: t r t f 3 ns) test condition ta = 25c ta 40 to 85c characteristics symbol v cc (v) typ. limit limit unit minimum pulse width (ck) t w (l) t w (h) ? 5.0 0.5 ? 5.0 5.0 ns minimum pulse width ( clr ) t w (l) ? 5.0 0.5 ? 5.0 5.0 ns minimum set-up time t s ? 5.0 0.5 ? 4.5 4.5 ns minimum hold time t h ? 5.0 0.5 ? 1.0 1.0 ns minimum removal time ( clr ) t rem ? 5.0 0.5 ? 2.0 2.0 ns
tc74vhct9273p/ft/fk 2009-07-01 5 ac characteristics (input: t r = t f = 3 ns) test condition ta = 25c ta = ? 40 to 85c characteristics symbol v cc (v) c l (pf) min typ. max min max unit 15 D 4.7 8.9 1.0 10.2 propagation delay time (ck-q) t plh t phl D 5.0 0.5 50 D 7.6 14.1 1.0 16.1 ns 15 D 7.5 14.4 1.0 16.4 propagation delay time ( clr -q) t phl D 5.0 0.5 50 D 10.4 19.6 1.0 22.3 ns 15 110 185 D 95 D maximum clock frequency f max D 5.0 0.5 50 70 100 D 60 D mhz output to output skew t oslh t oshl (note 1) 5.0 0.5 50 D D 1.0 D 1.0 ns input capacitance c in D D 4 10 D 10 pf power dissipation capacitance c pd (note 2) D 13 D D D pf note 1: parameter guaranteed by design. t oslh = |t plhm ? t plhn |, t oshl = |t phlm ? t phln | note 2: c pd is defined as the value of the internal equivalent capacitance which is ca lculated from the operating current consumption without load. average operating current can be obtained by the equation: i cc (opr) = c pd v cc f in + i cc /8 (per bit) and the total c pd when n pcs.of flip flop operate can be gained by the following equation: c pd (total) = 9 + 4n
tc74vhct9273p/ft/fk 2009-07-01 6 package dimensions weight: 1.30 g (typ.)
tc74vhct9273p/ft/fk 2009-07-01 7 package dimensions weight: 0.08 g (typ.)
tc74vhct9273p/ft/fk 2009-07-01 8 package dimensions weight: 0.03 g (typ.)
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